Radio frequency (RF) receivers often utilize an ‘integrate and dump’ function to demodulate a received RF signal. The ‘integrate and dump’ function essentially involves utilizing an integrator to generate an information (data) signal from a modulated RF signal using a local oscillator (LO). Once the information signal is demodulated, it is typically ‘dumped’ to a sample and hold circuit for further processing.
U.S. Pat. No. 6,587,072 (the “'072 Patent”) describes a radar based sensor system which includes two separate ‘integrate and dump’ portions, one for in-phase (I) signals, and one for quadrature (Q) phase signals. FIG. 1 of the '072 patent shows a first ‘integrate and dump’ portion (I Channel) formed by mixer 44, integrator 48, sampler 51, and switch 52, and another ‘integrate and dump’ portion (Q Channel) formed by mixer 45, integrator 47, sampler 51, and switch 54. Particularly, the ‘integrate’ is performed by the mixers 44, 45 and the integrators 47, 48, and the ‘dump’ is performed by the sampler 51 and the switches 52, 54. The sampler 51 provides a timing signal for actuating the switches 52, 54 at a rate commensurate with the frequency of the pulses received at the receiving antenna 31, so that all incoming pulses are detected. If this timing signal is somehow delayed, or offset, accurate detection of the pulses will not be accomplished.
Implementations of ‘integrate and dump’ type receivers often require very stringent timing signals. Such receivers often experience differential delay offsets due to, for example, layout differences between the circuit board including the source of the timing signal and the circuit board including the integrator. At lower frequencies and slower clock rates, differential delay offsets are less problematic. However, at higher frequencies and clock speeds, accurate timing signals are required for proper operation. High Resolution Radar (HRR) is an example of a high frequency application which utilizes an ‘integrate and dump’ function in the receiver circuitry. For example, the above-referenced '072 Patent details an exemplary HRR system.
FIG. 1 shows a conventional receiver circuit 100 which includes an ‘integrate and dump’ function (i.e., similar to either of the I or Q Channels described above with reference to the '072 Patent). The ‘integrate and dump’ function is provided by amplifier 120, resistor 130, capacitor 140, and switch 150. The mixer 110 correlates an input RF signal with a local oscillator (LO) signal to produce an analog information (data) signal at the input of the amplifier 120. This information signal is then amplified by the amplifier 120, and applied through the resistor 130 to charge the capacitor 140 while the switch 150 is open. The amplifier 120, resistor 130, and capacitor 140 thus form the ‘integrate’ portion of the ‘integrate and dump’ circuit. The opening and closing of the switch 150 is controlled by a timing pulse provided by a separate timing circuit (not shown). The ‘dump’ takes place when the switch 150 is closed and the capacitor 140 discharges into the sample and hold circuit 160. As will be noted by those of ordinary skill in the art, the proper alignment of the LO signal and the timing pulse is essential to maintaining maximum efficiency of the correlation process, and thus maximizing the signal to noise ratio (SNR). If the timing signal experiences differential delays, it will become out of phase alignment with the LO signal, and thus degrade the efficiency of the receiver.
Thus, there is presently a need for a receiver including an ‘integrate and dump’ function which does not experience differential delay offsets at high frequencies.